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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004, zarlink semiconductor inc. all rights reserved. features ? supports telcordia gr-1244-core stratum 4 and stratum 4e ? supports itu-t g.823 and g.824 for 2048 kbps and 1544 kbps interfaces ? supports ansi t1.403 and etsi ets 300 011 for isdn primary rate interfaces ? simple hardware control interface ? accepts two input references and synchronizes to any combination of 8 khz, 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz inputs ? provides a range of clock outputs: 1.544 mhz, 2.048 mhz, 16.384 mhz and either 4.096 mhz and 8.192 mhz or 32.768 mhz and 65.536 mhz ? provides 5 styles of 8 khz framing pulses ? holdover frequency accuracy of 1.5 x 10 -7 ? lock, holdover and selectable out of range indication ? selectable loop filter bandwidth of 1.8 hz or 922 hz ? less than 0.5 ns pp jitter on all output clocks ? external master clock source: clock oscillator or crystal applications ? synchronization and timing control for multi-trunk ds1/e1 systems such as dslams, gateways and pbxs ? clock and frame pulse source for st-bus, gci and other time division multiplex (tdm) buses ? line card synchronization for pdh systems june 2004 zl30100 t1/e1 system synchronizer data sheet figure 1 - functional block diagram reference monitor mode control virtual reference ieee 1149.1a feedback tie corrector enable state machine frequency select mux tie corrector circuit mode_sel1:0 tck ref1 rst ref_sel tie_clr c1.5o c4/c65o c8/c32o c16o f4/f65o f8/f32o f16o osco osci master clock tdo ref0 tdi tms trst holdover bw_sel hms lock ref_fail0 ref_fail1 dpll out_sel c2o e1 synthesizer ds1 synthesizer mux oor_sel ordering information ZL30100QDC 64 pin tqfp -40 c to +85 c
zl30100 data sheet 2 zarlink semiconductor inc. description the zl30100 t1/e1 system synchronizer contains a digi tal phase-locked loop (dpll), which provides timing and synchronization for multi-trunk t1 and e1 transmission equipment. the zl30100 generates st-bus and other tdm clock and framing signals that are phase locked to one of two input references. it helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference sw itching operations and during short periods when a reference is unavailable. the zl30100 is intended to be the central timing and synchronization resource for network equipment that complies with telcordia, etsi, itu-t and ansi network specifications.
zl30100 data sheet table of contents 3 zarlink semiconductor inc. 1.0 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 reference select multiplexer (mux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 reference monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 time interval error (tie) corrector circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 digital phase lock loop (dpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 frequency synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.0 control and modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 out of range selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 loop filter selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 output clock and frame pulse selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.1 freerun mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.2 holdover mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.3 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 reference selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.0 measures of performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 jitter generation (int rinsic jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 jitter tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 jitter transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 frequency accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 holdover accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 pull-in range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 lock range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8 phase slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.9 time interval error (tie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.10 maximum time interval error (mtie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.11 phase continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.12 lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.1 clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.2 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.0 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
zl30100 data sheet list of figures 4 zarlink semiconductor inc. figure 1 - functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - pin connections (64 pin tqfp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3 - reference monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4 - behaviour of the dis/requalify timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5 - ds1 mode out-of-range limits (oor_sel=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6 - e1 mode out-of-range limits (oor_sel=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7 - timing diagram of hitless reference switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8 - timing diagram of hitless mode switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9 - dpll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10 - mode switching in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11 - recommended power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12 - clock oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13 - crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14 - power-up reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15 - timing parameter measurement voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 16 - input to output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 17 - output timing referenced to f8/f32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
zl30100 data sheet 5 zarlink semiconductor inc. figure 2 - pin connections (64 pin tqfp) zl30100 34 36 38 40 42 44 46 48 64 62 60 58 56 52 50 54 16 14 12 10 8 6 4 2 osco nc gnd out_sel c1.5o mode_sel1 v dd av dd ic nc rst nc agnd f4/f65o v dd ref1 nc ic c8/c32o nc c2o agnd av dd nc f8/f32o c4/c65o ref_sel 18 20 22 24 26 30 32 28 c16o f16o tie_clr oor_sel ic osci av dd av dd av dd av core agnd agnd agnd nc nc ic ic mode_sel0 nc bw_sel ref0 v core lock hms trst gnd tdo tms holdover ic tck tdi v core av core gnd ref_fail0 ref_fail1
zl30100 data sheet 6 zarlink semiconductor inc. 1.0 pin description pin description pin # name description 1gnd ground. 0 v. 2v core positive supply voltage. +1.8 v dc nominal. 3lock lock indicator (output). this output goes to a logic high when the pll is frequency locked to the selected input reference. 4 holdover holdover (output). this output goes to a logic high whenever the pll goes into holdover mode. 5 ref_fail0 reference 0 failure indicator (output). a logic high at this pin indicates that the ref0 reference frequency has exceeded the out-of-ran ge limit set by the oor_sel pin or that it is exhibiting abrupt phase or frequency changes. 6ic internal bonding connection. leave unconnected. 7 ref_fail1 reference 1 failure indicator (output). a logic high at this pin indicates that the ref1 reference frequency has exceeded the out-of-ran ge limit set by the oor_sel pin or that it is exhibiting abrupt phase or frequency changes. 8tdo test serial data out (output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag scan is not enabled. 9tms test mode select (input). jtag signal that controls t he state transitions of the tap controller. this pin is internally pulled up to v dd . if this pin is not used then it should be left unconnected. 10 trst test reset (input). asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin should be pulsed low on power-up to ensure that the device is in the normal functional stat e. this pin is internally pulled up to v dd . if this pin is not used then it should be connected to gnd. 11 tck test clock (input): provides the clock to the jtag test logi c. if this pin is not used then it should be pulled down to gnd. 12 v core positive supply voltage. +1.8 v dc nominal. 13 gnd ground. 0 v. 14 av core positive analog supply voltage. +1.8 v dc nominal. 15 tdi test serial data in (input). jtag serial test instructions and data are shifted in on this pin. this pin is internally pulled up to v dd . if this pin is not used then it should be left unconnected. 16 hms hitless mode switching (input). the hms circuit controls phase accumulation during the transition from holdover or freerun mode to normal mode on the same reference. a logic low at this pin will cause the zl30100 to maintain the delay stored in the tie corrector circuit when it transitions from holdover or freerun mode to normal mode. a logic high on this pin will cause the zl30100 to measure a new delay for its tie corrector circuit thereby minimizing t he output phase movement when it transitions from holdover or freerun mode to normal mode. 17 mode_sel0 mode select 0 (input). this input combined with mode_sel1 determines the mode (normal, holdover or freerun) of operation, see table 4 on page 16. 18 mode_sel1 mode select 1 (input). see mode_sel0 pin description.
zl30100 data sheet 7 zarlink semiconductor inc. 19 rst reset (input). a logic low at this input resets the device. on power up, the rst pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. when the rst pi n goes high, the device will transition into a reset state for 3 ms. in the reset state all outputs will be forced into high impedance. 20 osco oscillator master clock (output). for crystal operation, a 20 mhz crystal is connected from this pin to osci. this output is not suitable for driving other devices. for clock oscillator operation, this pi n must be left unconnected. 21 osci oscillator master clock (input). for crystal operation, a 20 mhz crystal is connected from this pin to osco. for clock oscillator operation, this pin must be connected to a clock source. 22 ic internal connection. leave unconnected. 23 gnd ground. 0v. 24 nc no internal bonding connection. leave unconnected. 25 v dd positive supply voltage. +3.3 v dc nominal. 26 out_sel output selection (input). this input selects the signals on the combined output clock and frame pulse pins, see table 3 on page 16. 27 ic internal connection. connect this pin to ground. 28 ic internal connection. connect this pin to ground. 29 av dd positive analog supply voltage. +3.3 v dc nominal. 30 nc no internal bonding connection. leave unconnected. 31 nc no internal bonding connection. leave unconnected. 32 c1.5o clock 1.544 mhz (output). this output is used in ds1 applications. 33 agnd analog ground. 0 v 34 agnd analog ground. 0 v 35 av core positive analog supply voltage. +1.8 v dc nominal. 36 av dd positive analog supply voltage. +3.3 v dc nominal. 37 av dd positive analog supply voltage. +3.3 v dc nominal. 38 nc no internal bonding connection. leave unconnected. 39 nc no internal bonding connection. leave unconnected. 40 agnd analog ground. 0v 41 agnd analog ground. 0v 42 c4 /c65o clock 4.096 mhz or 65.536 mhz (output). this output is used for st-bus operation at 2.048 mbps, 4.096 mbps or 65.536 mhz (st-bus 65.536 mbps). the output frequency is selected via the out_sel pin. 43 c8/c32o clock 8.192 mhz or 32.768 mhz (output). this output is used for st-bus and gci operation at 8.192 mbps or for operation with a 32.768 mhz clock. the output frequency is selected via the out_sel pin. pin description (continued) pin # name description
zl30100 data sheet 8 zarlink semiconductor inc. 44 av dd positive analog supply voltage. +3.3 v dc nominal. 45 av dd positive analog supply voltage. +3.3 v dc nominal. 46 c2o clock 2.048 mhz (output). this output is used for standard e1 interface timing and for st-bus operation at 2.048 mbps. 47 c16o clock 16.384 mhz (output). this output is used for st-bus operation with a 16.384 mhz clock. 48 f8/f32o frame pulse (output). this is an 8 khz 122 ns active high framing pulse (out_sel=0) or it is an 8 khz 31 ns active high framing pulse (out_sel=1), which marks the beginning of a frame. 49 f4 /f65o frame pulse st-bus 2.048 mbps or st -bus at 65.536 mhz clock (output). this output is an 8 khz 244 ns active low fram ing pulse (out_sel=0), which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 2.048 mbps and 4.096 mbps. or this output is an 8 khz 15 ns active low framing pulse (out_sel=1), typically used for st-bus operation with a clock rate of 65.536 mhz. 50 f16o frame pulse st-bus 8.192 mbps (output). this is an 8 khz 61 ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 8.192 mbps. 51 agnd analog ground. 0v 52 ic internal connection. connect this pin to ground. 53 ref_sel reference select (input) . this input selects the input reference that is used for synchronization, see table 5 on page 18. this pin is internally pulled down to gnd. 54 nc no internal bonding connection. leave unconnected. 55 ref0 reference (input). this is one of two (ref0, ref1) input reference sources used for synchronization. one of five possible frequencies may be used: 8 khz, 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz. this pin is internally pulled down to gnd. 56 nc no internal bonding connection. leave unconnected. 57 ref1 reference (input). see ref0 pin description. 58 nc no internal bonding connection. leave unconnected. 59 ic internal connection. connect this pin to ground. 60 oor_sel out of range selection (input). this pin selects the out of range reference rejection limits, see table 1 on page 15. 61 v dd positive supply voltage. +3.3 v dc nominal. 62 nc no internal bonding connection. leave unconnected. 63 tie_clr tie corrector circuit reset (input). a logic low at this input resets the time interval error (tie) correction circuit re sulting in a realignment of t he input phase with the output phase. 64 bw_sel filter bandwidth selection (input). this pin selects the bandwidth of the dpll loop filter, see table 2 on page 16. set continuously high to track jitter on the input reference closely or set temporarily high to allow the zl 30100 to quickly lock to the input reference. pin description (continued) pin # name description
zl30100 data sheet 9 zarlink semiconductor inc. 2.0 functional description the zl30100 is a ds1/e1 system synchronizer providi ng timing (clock) and synchr onization (frame) signals to interface circuits for ds1 and e1 primary rate digital transmi ssion links, see table 1. figu re 1 is a functional block diagram which is described in the following sections. 2.1 reference sele ct multiplexer (mux) the zl30100 accepts two simultaneous reference input sig nals and operates on their rising edges. one of them, the primary reference (ref0) or the secondary referenc e (ref1) signal can be selected as input to the tie corrector circuit based on the refe rence selection (ref_sel) input. 2.2 reference monitor the input references are monitored by two independent reference monitor blocks, one for each reference. the block diagram of a single reference monitor is shown in figure 3. for each reference clock, the frequency is detected and the clock is continuously monitored for thr ee independent criteria that indicate abnormal behavior of the reference signal, for example; long term drif t from its nominal frequency or excessive jitter. ? reference frequency detector (rfd) : this detector determines whether the frequency of the reference clock is 8 khz, 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz and provides this information to the various monitor circuits and the phase detector circuit of the dpll. ? precise frequency monitor (pfm) : this circuit determines whether the frequency of the reference clock is within the applicable out-of-range limits selected by the oor_sel pin, see figure 5, figure 6 and table 1. it will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference. ? coarse frequency monitor (cfm) : this circuit monitors the reference frequency over intervals of approximately 30 s to quickly detect large frequency changes. ? single cycle monitor (scm) : this detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock. figure 3 - reference monitor circuit reference frequency detector single cycle monitor precise frequency monitor coarse frequency monitor dis/requalify timer ref0 / ref1 or or ref_dis= reference disrupted. this is an internal signal. mode select state machine holdover ref_dis ref_fail0 / ref_fail1
zl30100 data sheet 10 zarlink semiconductor inc. exceeding the thresholds of any of the monitors forces the corresponding ref_fail pin to go high. the single cycle and coarse frequency failure flags force the dpll into holdover mode and feed a timer that disqualifies the reference input signal when the failures are present for mo re than 2.5 s. the single cycle and coarse frequency failures must be absent for 10 s to let the timer requalify the input reference signal as va lid. multiple failures of less than 2.5 s each have an accumulative effect and will disqua lify the reference eventually. this is illustrated in figure 4. figure 4 - behaviour of the dis/requalify timer when the incoming signal returns to normal (ref_fail= 0), the dpll returns to normal mode with the output signal locked to the input signal. each of the monitors has a build-in hysteresis to prevent flickering of the ref_fail status pin at the thres hold boundaries. the precise frequency m onitor and the timer do not affect the mode (holdover/normal) of the dpll. figure 5 - ds1 mode out-of-range limits (oor_sel=0) 2.5 s 10 s current ref timer ref_fail scm or cfm failure holdover 0 ppm +32 ppm -32 ppm 0 51 83 64 c20 c20 32 32 -32 -96 -150 -100 0 -200 -50 50 150 200 frequency offset [ppm] out of range out of range out of range in range in range in range 0 0 c20 100 -64 -83 115 96 -32 -51 -115 c20: 20 mhz master clock on osci c20 clock accuracy
zl30100 data sheet 11 zarlink semiconductor inc. figure 6 - e1 mode out-of-range limits (oor_sel=1) 2.3 time interval error (tie) corrector circuit the tie corrector circuit eliminates phase transients on the output clock that may occur during reference switching or the recovery from holdover mode to normal mode. on the recovery from holdover mode (dependent on the hms pin) or when switching to another reference input, the tie corrector circuit measures the phase delay bet ween the current phase (feedback signal) and the phase of the selected reference signal. this delay value is stored in the tie corrector ci rcuit. this circuit creates a new virtual reference signal that is at the same phase position as t he feedback signal. by using th e virtual reference, the pll minimizes the phase transient it experiences when it switches to another reference input or recovers from holdover mode. the delay value can be reset by setting the tie corrector circuit clear pin (tie_clr ) low for at least 15 ns. this results in a phase alignment between the input reference si gnal and the output clocks and frame pulses as shown in figure 16 and figure 17. the speed of the phase alig nment correction is limited to 61 s/s when bw_sel=0. convergence is always in the direction of least phase trav el. in general the tie correction should not be exercised when holdover mode is entered for short time periods. tie_clr can be kept low continuously. in that case the output clocks will always be aligned with the selected input reference. this is illustrated in figure 7. 0 ppm +50 ppm -50 ppm 0 80 130 100 c20 c20 50 50 -50 -150 -150 -100 0 -200 -50 50 150 200 frequency out of range out of range out of range in range in range in range offset [ppm] 0 0 c20 100 -100 -130 180 150 -50 -80 -180 c20: 20 mhz master clock on osci c20 clock accuracy
zl30100 data sheet 12 zarlink semiconductor inc. figure 7 - timing diagram of hitless reference switching the hitless mode switching (hms) pin enables phase hitl ess returns from freerun and holdover modes to normal mode in a single reference operation. a logic low at the hms input disables the tie ci rcuit updating the delay value thereby forcing the output of t he pll to gradually move back to the original point before it went into holdover mode. (see figure 8). this prevents accumulation of phase in network elements. a logic high (hms=1) enables the tie circuit to update its delay value thereby preventing a la rge output phase movement after return to normal mode. this causes accumulation of phase in network elements. in both cases the pll?s output can be aligned with the input reference by setting tie_clr low. regardless of the hms pin state, reference switching in the zl30100 is always hitless unless tie_clr is kept low continuously. locked to ref1 ref0 output clock tie_clr = 1 tie_clr = 0 ref1 ref0 output clock ref1 locked to ref1 ref0 output clock ref1 ref0 output clock ref1 locked to ref0 locked to ref0
zl30100 data sheet 13 zarlink semiconductor inc. figure 8 - timing diagram of hitless mode switching examples: hms=1 : when 10 normal to holdover to normal mode transi tions occur and in each case the holdover mode was entered for 2 seconds, then the accumulated phase change (mtie) could be as large as 3.13 s. - phase holdover_drift = 0.15 ppm x 2 s = 300 ns - phase mode_change = 0 ns + 13 ns = 13 ns - phase 10 changes = 10 x (300 ns + 13 ns) = 3.13 s where: - 0.15 ppm is the accuracy of the holdover mode - 0 ns is the maximum phase discontinuity in the tr ansition from the normal mode to the holdover mode ref phase drift in holdover mode hms = 0 normal mode return to normal mode ref output clock ref output clock ref output clock phase drift in holdover mode normal mode return to normal mode output clock ref output clock ref output clock hms = 1 tie_clr =0 ref output clock tie_clr =0 ref output clock
zl30100 data sheet 14 zarlink semiconductor inc. - 13 ns is the maximum phase discontinuity in the tran sition from the holdover mode to the normal mode when a new tie corrector value is calculated. hms=0 : when the same 10 normal to holdover to normal mode changes occur and in each case holdover mode was entered for 2 seconds, then the overall mtie would be 300 ns. as the delay value for the tie corrector circuit is not updated, there is no 13 ns measurement error at this point. the phase can still drift for 300 ns when the pll is in holdover mode but when the pll enters normal mode again , the phase moves back to the original point so the phase is not accumulated. 2.4 digital phase lock loop (dpll) the dpll of the zl30100 consists of a phase detector, a limite r, a loop filter, a digitally controlled oscillator (dco) and a lock indicator, as shown in figure 9. the data path from the phase detector to the limiter is tapped and routed to the lock indicator that provides a lock indication which is output at the lock pin. figure 9 - dpll block diagram phase detector - the phase detector compares t he virtual reference signal from th e tie corrector circuit with the feedback signal and provides an error signal corresponding to the phase differ ence between the two. this error signal is passed to the limiter circuit. limiter - the limiter receives the error signal from the phas e detector and ensures that the dpll responds to all input transient conditions with a maximum output phase slope of 61 s/s or 9.5 ms/s, see table 2. loop filter - the loop filter is similar to a first order low pa ss filter with a narrow or wide bandwidth suitable to provide system synchronization or line card timing, see table 2. the wide bandw idth can be used to closely track the input reference in the pres ence of jitter or it can be temporarily enabl ed for fast locking to a new reference (1 s lock time). digitally controlled oscillator (dco) - the dco receives the limited and filt ered signal from the loop filter, and based on its value, generates a corresponding digital output signal. the synchroniza tion method of the dco is dependent on the state of the zl30100. state select from control state machine feedback signal from frequency select mux dpll reference to frequency synthesizer virtual reference from tie corrector circuit limiter loop filter digitally controlled oscillator phase detector lock indicator lock
zl30100 data sheet 15 zarlink semiconductor inc. in normal mode, the dco provides an output signal which is frequency and phase locked to the selected input reference signal. in holdover mode, the dco is free running at a frequenc y equal to the frequency that the dco was generating in normal mode. the frequency in holdover mode is calcul ated from frequency samples stored 26 ms to 52 ms before the zl30100 entered holdover mode. in freerun mode, the dco is free running with an accu racy equal to the accuracy of the osci 20 mhz source. lock indicator - the lock detector monitors if the output value of the phase detector is below a certain threshold value for a certain time. the selected phase threshold va lue guarantees the stable oper ation of the lock pin with the maximum network jitter on the reference input. if the dpll is locked and goes into holdover mode (auto or manual), the lock pin will in itially stay high for 1 s. if at that point the dpll is still in holdover mode, the lock pin will go low. in freerun mode the lock pin will go low immediately. 2.5 frequency synthesizers the output of the dco is used by the frequency synthesizers to generate the c1.5o, c2o, c4o , c8o, c16o, c32o and c65o clocks and the f4o , f8o, f16o , f32o and f65o frame pulses which are synchronized to the selected reference input (ref0 or ref1). the frequency synthesiz ers use digital techniques to generate output clocks and advanced noise shaping techniques to minimize the output jitter. the clock and frame pulse outputs have limited driving capability and should be buffered when driving high capacitance loads. 2.6 state machine as shown in figure 1, the control stat e machine controls the tie corrector ci rcuit and the dpll. the control of the zl30100 is based on the inputs mode_sel1:0, ref_sel and hms. 2.7 master clock the zl30100 can use either a clock or crystal as t he master timing source. fo r recommended master timing circuits, see the applications - master clock section. 3.0 control and modes of operation 3.1 out of range selection the frequency out of range limits for the precise frequency moni toring in the reference monitors are selected by the oor_sel pin, see table 1. oor_sel application applicable standard out of range limits 0 ds1 ansi t1.403 telcordia gr-1244-core stratum 4/4e 64 - 83 ppm 1e1 itu-t g.703 etsi ets 300 011 100 - 130 ppm table 1 - out of range limits selection
zl30100 data sheet 16 zarlink semiconductor inc. 3.2 loop filter selection the loop filter settings can be selected through the bw_sel pin, see table 2. 3.3 output clock and frame pulse selection the output clock and frame pulses of the frequency synthesizers are availabl e in two groups controlled by the out_sel input. table 3 lists the supported comb inations of output cl ocks and frame pulses. 3.4 modes of operation the zl30100 has three possible manual modes of operat ion; normal, holdover and freerun. these modes are selected with the mode select pins mode_sel1 and mode_sel0 as is shown in table 4. transitioning from one mode to the other is controlled by an external controller. 3.4.1 freerun mode freerun mode is typically used when an independent clock s ource is required, or i mmediately following system power-up before network synchronization is achieved. in freerun mode, the zl30100 provides timing and sync hronization signals which are based on the master clock frequency (supplied to osci pin) only, and are not synchronized to the reference input signals. the freerun accuracy of the out put clock is equal to the accuracy of the master clock (osci). so if a 32 ppm output clock is required, th e master clock must also be 32 ppm. see applications - se ction 5.2, ?master clock?. bw_sel detected ref frequency loop filter bandwidth phase slope limiting 0 any 1.8 hz 61 s/s 1 8 khz 58 hz 9.5 ms/s 1 1.544 mhz, 2.048 mhz, 8.192 mhz, 16.384 mhz 922 hz 9.5 ms/s table 2 - loop filter settings out_sel generated clocks generated frame pulses 0 c1.5o, c2o, c4o , c8o, c16o f4o , f8o, f16o 1 c1.5o, c2o, c16o, c32o, c65o f16o , f32o, f65o table 3 - clock and frame pulse selection mode_sel1 mode_sel0 mode 0 0 normal (with automatic holdover) 0 1 holdover 10 freerun 1 1 reserved (must not be used) table 4 - operating modes
zl30100 data sheet 17 zarlink semiconductor inc. 3.4.2 holdover mode holdover mode is typically used for short durations wh ile network synchronization is temporarily disrupted. in holdover mode, the zl30100 provides timing and synchr onization signals, which are not locked to an external reference signal, but are based on st orage techniques. the storage value is determined while the device is in normal mode and locked to an external reference signal. when in normal mode, and locked to the input refere nce signal, a numerical value corresponding to the zl30100 output reference frequency is stored al ternately in two memory locations ev ery 26 ms. when the device is switched into holdover mode, the value in memory from between 26 ms and 52 ms is used to set the output frequency of the device. the frequency accuracy of holdover mode is 0.15 ppm. two factors affect the accuracy of holdover mode. one is drift on the master clock while in holdover mode, drift on the master clock directly affects the holdover mode accu racy. note that the absolute master clock (osci) accuracy does not affect holdover accuracy, only the change in osci accuracy while in holdover mode. for example, a 32 ppm master clock may have a temperature coefficient of 0.1 ppm per c. so a 10 c change in temperature, while the zl30100 is in holdover mode may result in an additional offset (over the 0.15 ppm) in frequency accuracy of 1 ppm. which is much greater than the 0.15 ppm of the zl30100. the other factor affecting the accuracy is large jitter on the re ference input prior to the mode switch. 3.4.3 normal mode normal mode is typically used when a system clock sour ce, synchronized to the network is required. in normal mode, the zl30100 provides timing (c1.5o, c2o, c4o , c8o, c16o, c32 and c65o ) and frame synchronization (f4o , f8o, f16o , f32o and f65o ) signals, which are synchronized to one of the two reference inputs (ref0 or ref1). the input reference signal may have a nominal fre quency of 8 khz, 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz. the frequency of the reference inputs ar e automatically detected by the reference monitors. when the zl30100 comes out of reset while normal mode is selected by its mode_sel pins then it will initially go into holdover mode and generate clocks with the accura cy of its free running local oscillator (see figure 10). if the zl30100 determines that its selected reference is disrupt ed (see figure 3), it will remain in holdover until the selected reference is no longer disrupted or the external c ontroller selects another refer ence that is not disrupted. if the zl30100 determines that its selected reference is not di srupted (see figure 3) then the state machine will cause the dpll to recover from holdover via one of two paths depending on the logic level at the hms pin. if hms=0 then the zl30100 will transition directly to normal mode and it will align its output signals with its selected input reference (see figure 8). if hms=1 then the zl30100 will transition to normal mode via the tie correction state and the phase difference betw een the output signal s and the selected input re ference will be maintained. when the zl30100 is operating in normal mode, if it determ ines that its selected refe rence is disrupted (figure 3) then its state machine will cause it to automatically go to holdover mode. when the zl30100 determines that its selected reference is not disrupted then the state machine will cause the dpll to recover from holdover via one of two paths depending on the logic level at the hms pin (see figure 10). if hms=0 then the zl30100 will transition directly to normal mode and it will align its output signals with its input reference (see fi gure 8). if hms=1 then the zl30100 will transition to normal mode via the tie corr ection state and the phase difference between the output signals and the input refe rence will be maintained. if the reference selection changes because the val ue of the ref_sel1:0 pins changes, the zl30100 goes into holdover mode and returns to normal mode through the ti e correction state regardless of the logic value on hms pin. the zl30100 provides a wide bandwidth loop filter sett ing (bw_sel=1), which enables the pll to lock to an incoming reference in approximately 1 s.
zl30100 data sheet 18 zarlink semiconductor inc. figure 10 - mode switching in normal mode 3.5 refere nce selection the active reference input (ref0, ref1) is selected by t he ref_sel pin as shown in ta ble 5. if the logic value of the ref_sel pin is changed when and the dpll is in norm al mode, the zl30100 will perform a hitless reference switch. ref_sel (input pin) input reference selected 0ref0 1ref1 table 5 - reference selection ref_dis=1: current selected reference disrupted (see figure 3). this is an internal signal. ref_ch= 1: reference change, a change in the ref_sel pin. this is an internal signal. tie correction (holdover=1) holdover (holdover=1) ref_dis=0 ref_ch=1 ref_dis=0 and ref_dis=1 (ref_dis=0 and hms=1) or ref_ch=1 ref_dis=1 rst ref_ch=0 and hms=0 normal (holdover=0)
zl30100 data sheet 19 zarlink semiconductor inc. 4.0 measures of performance the following are some pll performance indi cators and their corresponding definitions. 4.1 jitter generation (intrinsic jitter) generated jitter is the jitter produced by the pll and is measured at its output. it is measured by applying a reference signal with no jitter to the input of the device, and measuring its ou tput jitter. generated jitter may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. generated jitter is usually measured with various bandlimiting filters depending on the applicable standards. 4.2 jitter tolerance jitter tolerance is a measure of the ability of a pll to oper ate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencie s) when jitter is applied to its reference. the applied jitter magnitude and jitter frequency depends on the applicable standards. 4.3 jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. i nput jitter is applied at va rious amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. for the zarlink digital plls two inter nal elements determine the jitter attenuat ion; the internal low pass loop filter and the phase slope limiter. the phase slope limiter limits the output phase slope to for example 61s/s. therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency i nput jitter, the maximum output phase slope will be limited (e.g., attenuated). since intrinsic jitter is always present, jitter attenuation will appear to be lowe r for small input jitter signals than for large ones. consequently, accurate jitter transfer functi on measurements are usually made with large input jitter signals (for example 75% of the spec ified maximum tolerable input jitter). 4.4 frequency accuracy the frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. 4.5 holdover accuracy the holdover accuracy is defined as the absolute frequenc y accuracy of an output clock signal, when it is not locked to an external reference signal, but is operat ing using storage techniques. for the zl30100, the storage value is determined while the device is in normal mode and locked to an external reference signal. 4.6 pull-in range also referred to as capture range. this is the input freq uency range over which the pll must be able to pull into synchronization. 4.7 lock range this is the input frequency range ov er which the synchronizer must be able to maintain synchronization.
zl30100 data sheet 20 zarlink semiconductor inc. 4.8 phase slope phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. the given signal is typically the output signal. the ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. anot her way of specifying the phase slope is as the fractional change per time unit. for example; a phase slope of 61 s/s can also be specified as 61 ppm. 4.9 time interval error (tie) tie is the time delay between a given ti ming signal and an ideal timing signal. 4.10 maximum time interval error (mtie) mtie is the maximum peak to peak delay between a give n timing signal and an ideal timing signal within a particular observation period. 4.11 phase continuity phase continuity is the phase difference between a given timi ng signal and an ideal timing signal at the end of a particular observation period. usually, the given timing signal and the ideal timing signal are of the same frequency. phase continuity applies to the output of the pll after a signal disturbance due to a reference switch or a mode change. the observation period is usually t he time from the disturbance, to just after the synchronizer has settled to a steady state. 4.12 lock time this is the time it takes the pll to frequency lock to t he input signal. phase lock occurs when the input signal and output signal are aligned in phase with respect to each othe r within a certain phase distance (not including jitter). lock time is affected by many factors which include: ? initial input to output phase difference ? initial input to output frequency difference ? pll loop filter bandwidth ? pll phase slope limiter ? in-lock phase distance the presence of input jitter makes it difficult to define when the pll is locked as it may not be able to align its output to the input within the required phase distance, dependen t on the pll bandwidth and the input jitter amplitude and frequency. although a short lock time is desirable, it is not always possible to achiev e due to other synchronizer requirements. for instance, better jitter transfer performance is achi eved with a lower frequency loop filter which increases lock time. and better (smaller) phase slope performa nce (limiter) results in longer lock times.
zl30100 data sheet 21 zarlink semiconductor inc. 5.0 applications this section contains zl30100 application specific details for power supply decoupling, reset operation, clock and crystal operation. 5.1 power supply decoupling it is recommended to place a 100 nf decoupling capacitor close to the power and ground pairs as shown in figure 11 to ensure optimal jitter performance. figure 11 - recommended power supply decoupling 100 nf 33 agnd 36 av dd 25 v dd 61 v dd 37 av dd v core 12 av core 35 gnd 1 av core 14 1.8 v 3.3 v 44 av dd 45 av dd 100 nf 100 nf 100 nf 29 av dd 41 agnd 51 agnd 23 gnd zl30100 100 nf 100 nf gnd 13 v core 2 100 nf 1 gnd 100 nf 100 nf 40 gnd 34 gnd 100 nf 100 nf
zl30100 data sheet 22 zarlink semiconductor inc. 5.2 master clock the zl30100 can use either a clock or cr ystal as the master timing source. za rlink application note zlan-68 lists a number of applicable osc illators and crystal s that can be used with the zl30100. 5.2.1 clock oscillator when selecting a clock oscillator, numerous parameters must be considered. this includes absolute frequency, frequency change over temperature, phase noise, output rise and fall times, output levels and duty cycle. the output clock should be connected directly (not ac co upled) to the osci input of the zl30100, and the osco output should be left open as shown in figure 12. figure 12 - clock oscillator circuit 5.2.2 crystal oscillator alternatively, a crystal oscillator may be used. a complete oscillator circuit made up of a crystal, resistor and capacitors is shown in figure 13. the accuracy of a crystal oscillator depends on the cryst al tolerance as well as the load capacitance tolerance. typically, for a 20 mhz crystal specified with a 32 pf load capacitance, each 1 pf change in load capacitance contributes approximately 9 ppm to the frequency deviat ion. consequently, capacitor tolerances, and stray capacitances have a major effect on the accuracy of the oscillator frequency. 1 frequency 20 mhz 2 tolerance as required 3 rise & fall time < 10 ns 4 duty cycle 40% to 60% table 6 - typical clock oscillator specification +3.3 v 20 mhz out gnd 0.1 f +3.3 v osco zl30100 osci no connection
zl30100 data sheet 23 zarlink semiconductor inc. the crystal should be a fundamental mode type - not an over tone. the fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. a typical crystal oscillator specification and circuit is shown in table 7 and figure 13 respectively. figure 13 - crystal oscillator circuit 5.3 power up sequence the zl30100 requires that the 3.3 v is not powered after the 1. 8 v. this is to prevent the risk of latch-up due to the presence of parasitic diodes in the io pads. two options are given: 1. power-up 3.3 v first, 1.8 v later 2. power up 3.3 v and 1.8 v simultaneously ensuring that the 3.3 v power is never lower than 1.8 v minus a few hundred millivolts (e.g., by using a schottky diode or controlled slew rate) 1 frequency 20 mhz 2 tolerance as required 3 oscillation mode fundamental 4 resonance mode parallel 5 load capacitance as required 6 maximum series resistance 50 ? table 7 - typical crystal oscillator specification osco 1 m ? 20 mhz zl30100 osci 100 ? 1 h the 100 ? resistor and the 1 h inductor may improve stability and ar e optional.
zl30100 data sheet 24 zarlink semiconductor inc. 5.4 reset circuit a simple power up reset circuit with about a 300 s re set low time is shown in figure 14. resistor r p is for protection only and limits current into the rst pin during power down conditions. t he reset low time is not critical but should be greater than 300 ns. figure 14 - power-up reset circuit +3.3 v rst r p 1 k ? c 10 nf r 10 k ? zl30100
zl30100 data sheet 25 zarlink semiconductor inc. 6.0 characteristics 6.1 ac and dc electr ical characteristics * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * voltages are with respect to ground (gnd) unless otherwise stated. * voltages are with respect to ground (gnd) unless otherwise stated. * supply voltage and operating temperature are as per recommended operating conditions. * voltages are with respect to ground (gnd) unless otherwise stated. absolute maximum ratings* parameter symbol min. max. units 1 supply voltage v dd_r -0.5 4.6 v 2 core supply voltage v core_r -0.5 2.5 v 3 voltage on any digital pin v pin -0.5 6 v 4 voltage on osci and osco pin v osc -0.3 v dd + 0.3 v 5 current on any pin i pin 30 ma 6 storage temperature t st -55 125 c 7 tqfp 64 pin package power dissipation p pd 241 mw 8 esd rating v esd 2 kv v recommended operating conditions* characteristics sym. min. typ. max. units 1 supply voltage v dd 2.97 3.30 3.63 v 2 core supply voltage v core 1.62 1.80 1.97 v 3 operating temperature t a -40 25 85 c dc electrical ch aracteristics* characteristics sym. min. max. units notes 1 supply current with: osci = 0 v i dds 3.0 6.5 ma outputs loaded with 30 pf 2 osci = clock, out_sel=0 i dd 32 42 ma 3 osci = clock, out_sel=1 i dd 42 61 ma 4 core supply current with: osci = 0 v i cores 022a 5osci = clocki core 14 20 ma 6 cmos high-level input voltage v cih 2v 7 cmos low-level input voltage v cil 0.8 v 8 input leakage current i il -3 3 a v i = v dd or 0 v 9 high-level output voltage v oh 2.4 v i oh = 10 ma 10 low-level output voltage v ol 0.4 v i ol = 10 ma
zl30100 data sheet 26 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * voltages are with respect to ground (gnd) unless otherwise stated. figure 15 - timing parameter measurement voltage levels * supply voltage and operating temperature are as per recommended operating conditions. ac electrical charact eristics* - timing parameter measur ement voltage levels (see figure 15) characteristics sym. cmos units notes 1 threshold voltage v t 1.5 v 2 rise and fall threshold voltage high v hm 2.0 v 3 rise and fall threshold voltage low v lm 0.8 v ac electrical charact eristics* - input timing for ref0 and ref1 references (see figure 16) characteristics symbol min. typ. max. units 1 8 khz reference period t ref8kp 121 125 128 s 2 1.544 mhz reference period t ref1.5p 338 648 950 ns 3 2.048 mhz reference period t ref2p 263 488 712 ns 4 8.192 mhz reference period t ref8p 63 122 175 ns 5 16.384 mhz reference period t ref16p 38 61 75 ns 6 reference pulse width high or low t refw 15 ns t ir, t or timing reference points all signals v hm v t v lm t if, t of
zl30100 data sheet 27 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. figure 16 - input to output timing ac electrical characteristi cs* - input to output timing for re f0 and ref1 references (see figure 16) characteristics symbol min. max. units 1 8 khz reference input to f8/f32o delay t ref8kd 0.7 2.0 ns 2 1.544 mhz reference input to c1.5o delay t ref1.5d 2.4 3.0 ns 3 1.544 mhz reference input to f8/f32o delay t ref1.5_f8d 2.5 3.3 ns 4 2.048 mhz reference input to c2o delay t ref2d 2.0 3.0 ns 5 2.048 mhz reference input to f8/f32o delay t ref2_f8d 2.2 3.3 ns 6 8.192 mhz reference input to c8o delay t ref8d 5.2 6.2 ns 7 8.192 mhz reference input to f8/f32o delay t ref8_f8d 5.5 6.3 ns 8 16.384 mhz reference input to c16o delay t ref16d 2.6 3.3 ns 9 16.384 mhz reference input to f8/f32o delay t ref16_f8d -28.0 -27.2 ns ref0/1 t refp t ref8kd , t ref_f8d t refw t refd t refw f8_32o output clock with the same frequency as ref
zl30100 data sheet 28 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. ac electrical char acteristics* - output timing (see figure 17) characteristics sym. min. max. units notes 1 c1.5o pulse width low t c1.5l 323.1 323.7 ns outputs loaded with 30 pf 2 c1.5o delay t c1.5d -0.6 0.6 ns 3 c2o pulse width low t c2l 243.2 243.8 ns 4 c2o delay t c2d -0.4 0.3 ns 5f4o pulse width low t f4l 243.5 244.2 ns 6f4o delay t f4d 121.5 122.2 ns 7c4o pulse width low t c4l 121.2 122.3 ns 8c4o delay t c4d -0.3 1.0 ns 9 f8o pulse width high t f8h 121.6 123.2 ns 10 c8o pulse width low t c8l 60.3 61.2 ns 11 c8o delay t c8d -0.4 0.2 ns 12 f16o pulse with low t f16l 60.6 61.1 ns 13 f16o delay t f16d 29.9 30.8 ns 14 c16o pulse width low t c16l 28.7 30.8 ns 15 c16o delay t c16d -0.5 1.4 ns 16 f32o pulse width high t f32h 30.0 31.8 ns 17 c32o pulse width low t c32l 14.8 15.3 ns 18 c32o delay t c32d -0.5 0.1 ns 19 f65o pulse with low t f65l 14.8 15.4 ns 20 f65o delay t f65d 7.1 8.0 ns 21 c65o pulse width low t c65l 7.2 8.1 ns 22 c65o delay t c65d -1.0 0.0 ns 23 output clock and frame pulse rise time t or 1.0 2.0 ns 24 output clock and frame pulse fall time t of 1.2 2.3 ns
zl30100 data sheet 29 zarlink semiconductor inc. figure 17 - output timing referenced to f8/f32o t f8h t f4d f4o c16o f8o t f16l f16o c8o c4o c2o t f16d t f4l t c16d t c8d t c4d t c1.5d t c16l t c8l t c4l t c2l t c1.5l t f32h c65o f32o t f65l f65o c32o t f65d t c65d t c32d t c65l t c32l f32o, c32o, f65o and c65o are drawn on a larger scale than the other waveforms in this diagram. t c2d c1.5o
zl30100 data sheet 30 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. 6.2 performance characteristics * supply voltage and operating temperature are as per recommended operating conditions. ac electrical char acteristics* - osci 20 mhz master clock input characteristics sym. min. max. units notes 1 oscillator tolerance -32 +32 ppm oor_sel=0 2 -50 +50 ppm oor_sel=1 3 duty cycle 40 60 % 4 rise time 10 ns 5 fall time 10 ns performance characteristics* - functional characteristics min. max. units notes 1 holdover accuracy 0.15 ppm 2 holdover stability 0 ppm deter mined by stability of the 20 mhz master clock oscillator 3 freerun accuracy 0 ppm determined by accuracy of the 20 mhz master clock oscillator 4 capture range -130 +130 ppm the 20 mhz master clock oscillator set at 0 ppm reference out of range threshold (including hysteresis) 5ds1 -64 -83 +64 +83 ppm the 20 mhz master clock oscillator set at 0 ppm 6e1 -100 -130 +100 +130 ppm the 20 mhz master clock oscillator set at 0 ppm lock time 7 1.8 hz loop filter 40 s 64 ppm frequency offset, bw_sel=0 8 58 hz and 922 hz loop filter 1 s 64 ppm frequency offset, bw_sel=1 output phase continuity (mtie) 9 reference switching 13 ns 10 switching from normal mode to holdover mode 0ns 11 switching from holdover mode to normal mode 13 ns output phase slope 12 1.8 hz filter 61 s/s bw_sel=0 13 58 hz and 922 hz filter 9.5 ms/s bw_sel=1
zl30100 data sheet 31 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * supply voltage and operating temperature are as per recommended operating conditions. * supply voltage and operating temperature are as per recommended operating conditions. performance characteristics* : output jitter generation - ansi t1.403 conformance signal ansi t1.403 jitter generation requirements zl30100 maximum jitter generation units jitter measurement filter limit in ui equivalent limit in the time domain ds1 interface 1 c1.5o (1.544 mhz) 8 khz to 40 khz 0.07 ui pp 45.3 0.20 ns pp 2 10 hz to 40 khz 0.5 ui pp 324 0.21 ns pp performance characteristics* : output jitter generation - itu-t g.812 conformance signal itu-t g. 8 1 2 jitter generation requirements zl30100 maximum jitter generation units jitter measurement filter limit in ui equivalent limit in the time domain e1 interface 1 c2o (2.048 mhz) 20 hz to 100 khz 0.05 ui pp 24.4 0.24 ns pp performance characteristics* - unfiltered intrinsic jitter characteristics max. [ui pp ] max. [ns pp ] notes 1 c1.5o (1.544 mhz) 0.0007 0.39 2 c2o (2.048 mhz) 0.0010 0.42 3c4o (4.096 mhz) 0.0017 0.37 4 c8o (8.192 mhz) 0.0035 0.39 5 c16o (16.384 mhz) 0.0091 0.45 6 c32o (32.768 mhz) 0.015 0.39 7 c65o (65.536 mhz) 0.032 0.41 8f4o (8 khz) 0.40 9 f8o (8 khz) 0.29 10 f16o (8 khz) 0.35 11 f32o (8 khz) 0.30 12 f65o (8 khz) 0.34
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